Modern electronic devices are often made up of large numbers of sub-components such as latches and gates, embodied in transistors, which frequently number in the millions. In some cases, the functional design of an electrical or electronic device includes electrical paths that converge in a logic structure into a single output. This is especially true for devices in early stages of the development cycle, before optimization and refinement of the design.
Modern very large scale integrated circuit (VLSI) systems typically include various components included to ensure robust designs. For example, design engineers typically include design for test (DFT) mechanisms in modern VLSI designs. DFT mechanisms typically support a variety of testing and verification tools.
For example, one of the most common testing methods is stuck-at-fault (SAF) testing. Broadly, SAF testing seeks to identify logic and/or electrical faults in the design that cause stuck-at faults. Generally, stuck-at faults are faults that cause a node and/or output to remain in a constant state, instead of varying according to the inputs of the upstream logic. That is, instead of producing a “1” or a “0”, based on the desired behavior, a stuck-at fault produces only a “1” or a “0”, regardless of the desired behavior. The logic value at that node is ‘stuck” either high (stuck-at-one (sa1)) or low (stuck-at-zero(sa0)).
SAF testing, as well as many other types of testing, frequently uses test patterns that are intended for a particular circuit design and/or to test for one or more particular conditions. Generally, the test system applies the test pattern(s) as an input to the circuit under test and compares the circuit output with a known good result. Because the number of possible test required can be very large, on the order of 2n possible input combinations, typical systems use random test pattern generators to generate the input test patters for a particular design.
In most cases, these randomly-generated test patterns are effective for identifying many types of faults. For many faults, a randomly-generated test pattern yields the required inputs to cover the majority of operational conditions and expected input combinations. However, there are certain situations where a randomly generated test patter does not yield all of the desired input combinations. For example, there are certain structures, such as large AND or OR trees where there is a very low probability that test pattern generator will produce a suitable input pattern required to test a particular SAF for that AND/OR tree. These SAFs are often referred to as “random pattern resistant” faults.
In many cases, random pattern resistant faults require the design engineer to rework the behavioral and/or structural layout of a design. However, the hardware description language (HDL) representation of the entire design tends to change frequently, especially in the earlier stages of development. As such, even if the designer does eliminate the random pattern resistant fault, the effort may be wasted when a design revision changes the HDL representation such that what was once an optimal overall solution is no longer optimal. Moreover, the design engineer may not be aware of the fault until after synthesis of the design.
That is, in typical systems, one a design was through the synthesis step in the design process, the design engineer would run a ‘fault coverage’ reporting tool on the design. If the tool identifies random pattern resistant faults, the design engineer must either manually correct the physical design, or, more frequently, modify the HDL to improve testability with the design. Once modified, the design engineer still had to apply synthesis and other testing tools to look for faults caused or revealed by the correction. These reiterations add costly delay and expense into the design process.